On Generating High Quality Tests for Transition Faults
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چکیده
ATS 2002 Integrated Test Scheduling, Test Parallelization and TAM Design Erik Larsson, Klas Arvidsson, Hideo Fujiwara and Zebo Peng On Generating High Quality Tests for Transition Faults Yun Shao, Irith Pomeranz and Sudhakar M. Reddy A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design Tomoo Inoue, Tomokazu Miura, Akio Tamura, and Hideo Fujiwara Test Scheduling and Test Access Architecture Optimization for System-on-Chips Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang Test Scheduling of BISTed Memory Cores for SOC Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, and Chen-Wen Wu A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuit Marong Phadoongsidhi, Kim T. Le, and Kewal K. Saluja
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تاریخ انتشار 2002